Diffusion Defectivity Test

 Diffusion related damage can create defects and can often be a serious yield problem for many types of heavy dopants utilized for buried layers, source drains, etch stops and other diffusions requiring maximum dopant penetration into the silicon substrate.


Many defects are very visual in photolithography and etch, but diffusion defects are often hidden in the underlying crystal lattice.  Diffusion related damage can create defects and can often be a serious yield problem for many types of heavy dopants utilized for buried layers, source drains, etch stops and other diffusions requiring maximum dopant penetration into the silicon substrate. Here we outline a methodology to decorate these defects in order to perform a quantitative microscopic comparison between source materials provided by Desert Silicon Inc. and those provided by other suppliers. Our customers have told us repeatedly that our products have significantly less diffusion related damage in comparison to products provided by other suppliers. Here, we teach you how to make the comparison within your own organization.

Rick Smyer, manager of the Discrete Pilot Line for Motorola’s Semiconductor Products Division stated “the wafers I ran with your arsenic spin-on glass are now the standard for our line.”

Bob Howard, Engineering Manager of Lansdale Semiconductor, stated “your products are the best on the market with far less diffusion related damage than the competition.” Lansdale has utilized a wide variety of materials from Desert Silicon including As, Sb, B, P, Al, In, Ga, and undoped products.

Preston Sykes, manager of Motorola’s Materials group utilized our antimony and arsenic products for buried layer diffusions and stated “I don’t know what’s going on with the current suppliers but your products have significantly less damage and we will be diffusing with those now.”

Local diode company’s Process Engineering Manager, “after 35,000 hours of life testing, there has been zero failures using Desert Silicon’s SOG products. Desert Silicon makes the best products on the market.”

This process outline will enable you and your organization to “take the waste test”. We encourage you to do the comparison and see for yourself how yields can be increased, translating to significant increase in profit margins and less waste. Our products can significantly reduce antimony flowers, arsenic rosettes, diffusion related oxidation induced stacking faults, and other types of defects. Often, it only takes one of these defects to destroy an entire die.

1.0 Purpose

This procedure covers the necessary actions for delineating diffusion related defects including antimony flowers, arsenic rosettes, diffusion related oxidation induced stacking faults, and other diffusion related defects.

2.0 Safety

Designated wafer processing employees are responsible for being familiar with the requirements for safe handling of chemical products or materials. Extreme caution is to be utilized when handling or processing chemicals, especially HF containing mixtures. Working with HF without taking proper precautions may well severely injure or even kill you. Make sure the proper precautions are taken.

3.0 Procedure
3.1Preparation Steps

  • 3.1.1 Create a check list with the following information recorded: Process technicians name, diffusion run log record#, wafer lot#; pre-deposition and, drive in conditions including time, temp, push/pull rate; ramping information, ambient gas flows; sheet resistance; junction depth, spin on dopant used and the ID of wafers for evaluation.
  • 3.1.2 Strip the SOG/oxide completely off of the wafers that have been through pre deposition and drive in to be evaluated for diffusion related damage by using BOE (buffered oxide etch) followed by rinsing in UPDI (ultrapure deionized water) to 18-megohm resistivity.
  • 3.1.3 Spin rinse/dry or blow dry wafers with N2.
  • 3.1.4 Be sure that all data for sheet resistance and junction depth are measured and collected prior to any of the decoration etches.

3.1.5   Wright etch is generally the preferred defect decoration etchant as it is less dependent upon the wafer type, dopant, and orientation to achieve results.  Wright Etch is a preferential etch for revealing defects in (100) and (111) oriented, p- and n-type silicon. The Wright etch reveals clearly defined oxidation induced stacking faults, dislocations, swirls, and striations with minimum surface roughness or extraneous (artifactual) pitting. These defects are known causes of shorts and current leakage in finished semiconductor devices when they fall across isolated junctions. A relatively slow etch rate (~1 um of silicon per minute) at room temperature provides etch control. The long shelf life of this etchant allows the solution to be stored in reasonable quantities. Commercially available etch can be utilized or the following can be mixed if appropriate mixing facilities are available.

3.1.6   Typically the etch time is about five minutes.  For the best defect definition the etch time may be optimized longer or shorter.  After etch is completed, again rinse in UPDI (ultra-pure deionized water) to 18-megohm resistivity.

3.1.7   Spin rinse/dry or blow dry wafers with N2.
3.2   Defect Analysis

  • 3.2.1   Defect analysis can be performed using Optical Nomarski Microscopy, also known as Differential interference contrast microscopy (DIC), and as Nomarski Interference Contrast (NIC) is an optical microscopy illumination technique used to enhance the contrast in unstained, transparent or semitransparent samples. It is in effect a way to see defects in 3 dimensions. Defects can easily be observed and quantified (# of defects/mm2). A typical sampling method is to do a diameter scan and count defects across the scan.  This can be done initially using relatively low power (100-500X) to get a defect count across the slice.  The area for the scan across the wafer is shown below:

Table 1. Square millimeters in a diameter scan across a wafer

100X 250X 500X
100mm Wafer 180 mm2 72 mm2 36 mm2
150mm Wafer 270 mm2 108 mm2 54 mm2
200mm Wafer 360 mm2 144 mm2 72 mm2
300mm Wafer 540 mm2 216 mm2 108 mm2

To determine defects per mmdivide number of defects found in a scan by the area shown in the table above. For example if you find 6 defects in a diameter scan on a 150 mm wafer at 250X you would have:  6 defects / 108 mm2 = 0.056 defects /mm2.  Multiple scans can be done across one or more wafer to get an average for the scans.

  • 3.2.2   Desert Silicon recommends 2% O2 in N2 ambient will achieve very low quantities of defects. To obtain more qualitative information about the type of defects, utilize the 500-1000X optical air/oil lenses whereby oxidation induced stacking faults, threading dislocations, and many other defect types can be discerned one from another. To further quantify, the SEM and TEM methods can be utilized.
  • 3.2.3   Scanning Electron Microscopy (SEM) will require the additional sample preparation techniques of breaking, casting, and polishing the cast sample.
  • 3.2.4   Transmission Electron Microscopy (TEM) will also require additional sample preparation including thinning the material sufficiently for TEM imaging.
  • 3.3    Materials can be compared directly by the defects per square millimeter.

4.0 Invitation

Take The Diffusion Defect Test and compare your current supplier to Desert Silicon Inc. We invite our customers to utilize the above analytical techniques to compare Desert Silicon Inc. spin-on dopant materials with those of the competition. We are certain that you will find less damage that directly translates to increased yield for your product lines.